Compact modeling and fast simulation of on-chip interconnect lines

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This publication ranks between 9998979695949392919089888786858483828180797877767574737271706968676665646362616059585756555453525150494847464544434241403938373635343332313029282726252423222120191817161514131211109876543210% and 100999897969594939291908988878685848382818079787776757473727170696867666564636261605958575655545352515049484746454443424140393837363534333231302928272625242322212019181716151413121110987654321% of publications that I have read in terms of scientific quality and importance.

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